1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to techniques for enhancing the overall process flow by considering characteristics of the back side of substrates during various manufacturing stages.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate material. One prominent type of semiconductor material is silicon, since the majority of semiconductor devices including highly complex electronic circuits is currently, and in the foreseeable future will be, manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable carriers for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs) and the like. The individual integrated circuits are arranged in an array form, wherein most of the manufacturing steps, which may add up to 500-1000 and more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for a few processes, such as photolithography processes, certain metrology processes, packaging of the individual devices after dicing the substrate and the like. Thus, economic constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size so as to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In the attempt to maximize the useful surface area for a given substrate size, the peripheral chips are positioned as closely to the substrate perimeter as it is compatible with substrate handling processes. Generally, most of the manufacturing processes are performed in an automated manner, wherein the substrate handling is performed at the back side of the substrate and/or the substrate edge, which typically includes a bevel at least at the front side of the substrate.
The fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in a material layer located on the front side of the substrate. These tiny regions of precisely controlled size are generated by patterning the material layer by performing lithography, etch, implantation, deposition, oxidation processes and the like, wherein each of the corresponding processes has to be performed within strictly defined process windows. That is, the result of a patterning process may depend on the layer thickness of the deposition process, the quality of the lithography process, the fidelity of the etch process and the like. As an example of a highly complex manufacturing sequence, the fabrication of a gate electrode of a field effect transistor may be referred to, which represents an important component of modern digital circuits. Since the dimensions of the field effect transistor substantially determine operating speed and packing density of the integrated circuit, the patterning of the gate electrode is a highly critical process stage. In well-established MOS technologies, the critical gate forming process may include the formation of an appropriate gate insulation layer followed by the deposition of a gate electrode material and possible further materials, such as anti-reflective coating (ARC), required for the subsequent lithography process. Typically, at least a mask layer may be formed above the gate material layer, which may consist of or may be formed by means of a layer of photoresist that is patterned by the photolithography process. During the photolithographic process, the resist may be spin-coated onto the surface and then selectively exposed to ultraviolet radiation through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Based on this resist pattern, the actual gate patterns may be formed by a complex etch sequence. Since the dimensions of the gate electrodes in sophisticated integrated micro-structure devices are steadily decreasing, the equipment used for forming the gate electrodes have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. For example, the ability of the exposure process to create minute resist features may depend on critical parameters, such as numerical aperture, depth of focus and wavelength of the light source used. Consequently, modern lithography tools may have a reduced depth of focus, thereby requiring precisely defined layer thicknesses as well as accurate mechanical positioning of the substrate. As previously explained, substrate handling, supporting and positioning is typically accomplished by contacting the back side of the substrate by vacuum grippers, wafer chucks and the like. Hence, although the actual patterning process occurs at the front side of the substrate, the characteristics of the back side may also have a significant effect on the process result, in particular, when highly scaled devices are considered. For example, the presence of particles on the back side may result in defocused exposure fields due to the reduced depth of focus.
Also, in other process stages, the status of the back side may have an important influence on the processes performed at the front side. For instance, at the final phase of the manufacturing process of integrated circuits, solder bumps are typically provided, a metallization is formed on the back side and the separated die are attached to appropriate packages. In this sequence, surface characteristics, such as surface roughness, defectivity, chemical composition and the like, may represent important factors. In conventional process strategies, these factors may be difficult to be controlled, since many of the processes, such as deposition processes, wet chemical processes and the like, may also affect the back side of the substrate, however, in a highly unpredictable manner. For example, the deposition of the gate electrode material, which is frequently provided in the form of polysilicon, may be performed on the basis of a furnace process in a controlled ambient, to which is also exposed the substrate back side, resulting in the deposition of polysilicon also on the back side. Other deposition processes may be chemical vapor deposition (CVD), physical vapor deposition (PVD) and the like, which may result in a highly unpredictable coverage of portions of the back side, thereby affecting subsequent processes in a highly uncontrollable manner. Consequently, with increasing dimensions of the substrates used in fabricating microstructures and the continuous demand for reduced critical dimensions of the individual features, the characteristics of the substrate back side may have an increasing influence on production yield, wherein presently practiced process strategies may suffer from insufficient controllability of the properties of the substrate back side.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.